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A CMOS single-chip direct conversion satellite receiver for digital broadcasting system

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10 Author(s)
Bo-Eun Kim ; Integrant Technol. Inc., Kyeongki, South Korea ; Se-Yeob Kim ; Tae-Ju Lee ; Jin-Kyu Lim
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This paper presents a fully integrated single-chip direct conversion receiver for DBS system. The receiver tunes 950-2150 MHz wide band using integrated low phase noise VCOs and a fractional-N phase locked loop. Fully programmable 2-58 MHz cut-off frequency channel select filter effectively eliminates out-of-channel jammers to increase the linearity and optimize its performance for the 1-45 Msps variable data rates. A delta-sigma modulated fractional-N synthesizer with low noise quadrature VCOs exhibits phase noise of -76 dBc/Hz at 10 kHz offset. It has a -65 dBm sensitivity with an 80 dB system gain dynamic range. The receiver draws only 100 mA from 1.8 V supply. This low power highly integrated DBS receiver uses a 0.18 /spl mu/m CMOS process.

Published in:

VLSI Circuits Digest of Technical Papers, 2002. Symposium on

Date of Conference:

13-15 June 2002

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