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Design optimizations of a high performance microprocessor using combinations of dual-V/sub T/ allocation and transistor sizing

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9 Author(s)
Tschanz, J. ; Microprocessor Res., Intel Labs., Hillsboro, OR, USA ; Yibin Ye ; Liqiong Wei ; Govindarajulu, V.
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Joint optimizations of dual-V/sub T/ allocation and transistor sizing reduce low-V/sub T/ usage by 36%-45% and leakage power by 20% in a high performance microprocessor, with minimal impact on total active power and die area. An enhancement of the optimum design allows processor frequency to be increased efficiently during manufacturing.

Published in:

VLSI Circuits Digest of Technical Papers, 2002. Symposium on

Date of Conference:

13-15 June 2002