By Topic

Design optimizations of a high performance microprocessor using combinations of dual-V/sub T/ allocation and transistor sizing

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

9 Author(s)
J. Tschanz ; Microprocessor Res., Intel Labs., Hillsboro, OR, USA ; Yibin Ye ; Liqiong Wei ; V. Govindarajulu
more authors

Joint optimizations of dual-V/sub T/ allocation and transistor sizing reduce low-V/sub T/ usage by 36%-45% and leakage power by 20% in a high performance microprocessor, with minimal impact on total active power and die area. An enhancement of the optimum design allows processor frequency to be increased efficiently during manufacturing.

Published in:

VLSI Circuits Digest of Technical Papers, 2002. Symposium on

Date of Conference:

13-15 June 2002