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Selective node engineering for chip-level soft error rate improvement [in CMOS]

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6 Author(s)
Karnik, T. ; Circuit Res., Intel Labs., Hillsboro, OR, USA ; Vangal, S. ; Veeramachaneni, V. ; Hazucha, P.
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This paper presents a technique to selectively engineer sequential or domino nodes in high performance circuits to improve soft error rate (SER) induced by cosmic rays or alpha particles. In 0.18 /spl mu/m process, the SER improvement is as much as 3/spl times/ at the cell-level, 1.8/spl times/ at the block-level and 1.3/spl times/ at the chip-level without any penalty in performance or area, and <3% power penalty. The node selection, hardening and SER quantification steps are fully automated.

Published in:

VLSI Circuits Digest of Technical Papers, 2002. Symposium on

Date of Conference:

13-15 June 2002