A 4 GHz 130 nm address generation unit with 32-bit sparse-tree adder core

This paper describes a 32-bit Address Generation Unit (AGU) designed for 4 GHz operation in 1.2 V, 130 nm technology. The AGU utilizes a 152 ps dual-V, sparse-tree adder core to achieve 20% delay reduction, 80% lower interconnect density and a low (1%) active energy leakage component. The semidynamic implementation enables an average energy profile similar to static CMOS, with good sub-130 nm scaling trend.