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SOI-optimized 64-bit high-speed CMOS adder design

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4 Author(s)
Jae-Joon Kim ; Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA ; Joshi, R. ; Ching-Te Chuang ; Roy, K.

Presents a high-speed 64-bit hybrid carry-lookahead/carry-select adder in 0.1 /spl mu/m partially depleted silicon-on-insulator (PD/SOI) technology with a critical path delay of 346 ps. Sense-amplifier based differential logic with source follower evaluation tree is used for fast generation of 8-bit group carry. Floating body PD/SOI shows 24% performance improvement over bulk CMOS for the 8-bit group carry generating circuit. We also show that the proposed circuit is robust to noise induced by floating body effect in PD/SOI.

Published in:

VLSI Circuits Digest of Technical Papers, 2002. Symposium on

Date of Conference:

13-15 June 2002