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A 110 nm 512 Mb DDR DRAM with vertical transistor trench cell

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20 Author(s)
Wuensche, S. ; Infineon Technol., Essex Junction, VT, USA ; Jacunski, M. ; Streif, H. ; Sturm, A.
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This paper describes a 512 Mb DDR SDRAM in 110 nm technology based on a highly cost efficient 8F/sup 2/ trench capacitor cell with a double gate vertical pass transistor. The product also features a bitline voltage generator using a distributed output transistor with a power supply IR-drop correction scheme. A read/write selective column activation circuit is employed to optimize high frequency operation.

Published in:

VLSI Circuits Digest of Technical Papers, 2002. Symposium on

Date of Conference:

13-15 June 2002