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A monolithic CMOS 10.4-GHz phase locked loop

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2 Author(s)
Dong-Jun Yang ; Dept. of Electr. & Comput. Eng., Florida Univ., Gainesville, FL, USA ; O, K.

A 10.4-GHz PLL with a 256/257 dual modulus prescaler implemented in a 0.18-/spl mu/m CMOS process is presented. The prescaler with a 4/5 synchronous counter operates up to 14 GHz. The counter achieves this by using feedback. The phase noise levels of the PLL and VCO at a 3-MHz offset with I/sub VCO/=8.1 mA are -122 dBc/Hz. The PLL operates between 9.7 10.4 GHz, while drawing 34 mA at V/sub DD/=1.8 V.

Published in:

VLSI Circuits Digest of Technical Papers, 2002. Symposium on

Date of Conference:

13-15 June 2002