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Reliability improvement of Cu/low-k dual damascene interconnects using the depo/etch barrier process by newly developed I-PVD

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6 Author(s)
Motoyama, K. ; ULSI Device Dev. Div., NEC Corp., Sagamihara, Japan ; Faguet, J. ; Katsuki, J. ; Chung, G.
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We have developed a barrier deposition process, called the depo/etch barrier process. The depo/etch barrier process is a barrier deposition process followed by an Ar etching process to remove the barrier film at the via bottom. A newly developed I-PVD tool was designed for realizing the depo/etch process by performing both deposition and etching in the same chamber. We applied the depo/etch barrier using the I-PVD tool to Cu/low-k dual damascene interconnects, and achieved a lowering of via resistance and higher endurance against EM and yield-drop with thermal cycles by the removal of the via bottom barrier.

Published in:

Interconnect Technology Conference, 2002. Proceedings of the IEEE 2002 International

Date of Conference:

2002