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Many recent DSP applications (3G wireless and beyond) use various linear algebra operations to implement required algorithms. These algorithms depend on high data throughput and high-speed computations for real-time performance. Parallel array processing presents a viable computing arrangement for solving such tasks. In the authors' opinion, the system-on-chip, all-in-one approach to parallel digital signal processing combining the homogeneous processor array with large amounts of data memory will be the core of future embedded digital signal processing applications. We present a modification of a general linear algebra system-solving algorithm that is suitable for SoC implementations. Higher integration and operating frequencies are achievable due to the elimination of long and wide feedback paths, when successively implementing this algorithm. Modification is based on programmable processor array with multithreaded systolic computation capability.