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A novel asymmetric gate recess process for InP HEMTs

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4 Author(s)
Robin, Franck ; Lab. for Electromagn. Fields & Microwave Electron., Swiss Fed. Inst. of Technol., Zurich, Switzerland ; Meier, H. ; Homan, O.J. ; Bachtold, W.

An asymmetric gate recess process has been developed for the fabrication of InP-based HEMTs with improved breakdown voltage. This process is based on a double e-beam exposure of a 4-layers stack of PMGI and PMMA resists. Vertical patterns can be fabricated that can otherwise not be achieved with standard e-beam lithography processes. A 30% improvement of the on-state breakdown voltage of 0.2 μm InP HEMTs was obtained without marked degradation of fmax.

Published in:

Indium Phosphide and Related Materials Conference, 2002. IPRM. 14th

Date of Conference:

2002