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A high performance lattice architecture of 2D discrete wavelet transform for hierarchical image compression

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2 Author(s)
Taegeun Park ; Comput. & Electron. Eng., Catholic Univ. of Korea, Bucheon, South Korea ; Sunkyung Jung

This paper presents a high performance lattice architecture of 2D discrete wavelet transform (DWT), which is scalable to extend to an arbitrary 2D DWT with M taps and J levels. The proposed lattice structure fits in a VLSI implementation due to its regularity and shows the period of N/sup 2//2 to compute an N/spl times/N image because the even and odd rows are processed simultaneously.

Published in:

Consumer Electronics, 2002. ICCE. 2002 Digest of Technical Papers. International Conference on

Date of Conference:

18-20 June 2002