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A low-cost media-processor based real-time MPEG-4 video decoder

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4 Author(s)
Jin-Hau Kuo ; Dept. of Comput. Sci. & Inf. Eng., Nat. Taiwan Univ., Taipei, Taiwan ; Ja-Ling Wu ; Jim Shiu ; Kan-Li Huang

In this paper by implementing a realistic MPEG-4 core profile decoder over the TriMedia/spl trade/ DSP chip, we investigate a series of important issues related to the use of a media-processor to satisfy multimedia compression and processing requirements. The realistic MPEG-4 decoder optimized implementation by this DSP chip can support resolutions up to 4 CIF (720/spl times/576) at 30 fps. The issues we investigated include the overview of characteristics of media-processor architecture, the speedup of the MPEG-4 decoder based on the TriMedia/spl trade/ DSP chip, multimedia co-processor or hardware accelerator based approaches, Very Long Instruction Word (VLIW) and Single Instruction Multiple Data (SIMD) programming technique and the media-processor based solution for set-top box applications.

Published in:

Consumer Electronics, 2002. ICCE. 2002 Digest of Technical Papers. International Conference on

Date of Conference:

18-20 June 2002