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A new built-in TPG method for circuits with random pattern resistant faults

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4 Author(s)
X. Kavousianos ; Dept. of Comput. Eng. & Inf., Patras Univ., Greece ; D. Bakalis ; D. Nikolos ; S. Tragoudas

The partition of the inputs of a circuit under test (CUT) into groups of compatible inputs reduces the size of a test pattern generator and the length of the test sequence for built-in self-test (BIST) applications. In this paper, a new test-per-clock BIST scheme is proposed which is based on multiple input partitions. The test session consists of two or more phases, and a new grouping is applied during each test phase. Using the proposed method a CUT can be tested at-speed and complete fault coverage (100%) is achieved with a small number of test vectors and small area overhead. Our experiments show that the proposed technique compares favorably to the already known techniques

Published in:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  (Volume:21 ,  Issue: 7 )