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A comprehensive approach to the partial scan problem using implicit state enumeration

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2 Author(s)
P. Kalla ; Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA ; M. Ciesielski

This paper presents a novel technique to evaluate the noncontrollability measures of state registers for partial scan design. Our model uses implicit techniques for finite state machine (FSM) traversal to identify noncontrollable state registers. By implicitly enumerating the states of a machine, we accurately evaluate the noncontrollability of flip-flops by determining exactly what values can or cannot be stored or are difficult to store in the state registers. By doing so, we not only target the untestable faults due to state unreachability of the machine but also the difficult-to-test faults caused by difficult-to-control flip-flops. The values observed in the flip-flops during the implicit FSM traversal are used to evaluate flip-flop controllability measures to support the testability analysis. This technique is programmed as an algorithm called SIMPSON and the authors analyze its effectiveness by carrying out extensive experiments over a large set of MCNC and ISCAS benchmarks. For large circuits, implicit state enumeration becomes infeasible because of computer memory and time limitations. To overcome these limitations, we propose the use of approximate reachability analysis of the circuit to estimate the noncontrollability of state registers. By partitioning a large FSM into smaller sub-FSMs, and implicitly traversing the individual submachines, the reachable state set can be overapproximated as a product of smaller subsets. The values observed in the flip-flops of the submachines during the approximate FSM traversal facilitates the estimation of their noncontrollability measures. An algorithm called SAMSON is proposed for this purpose and its effectiveness is illustrated over some of the larger circuits in the ISCAS benchmark suite. The results demonstrate the superiority of the authors' method over conventional state-of-the-art scan register selection techniques in terms of higher fault coverage achieved by selecting fewer, or an equal number, of partial scan registers

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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  (Volume:21 ,  Issue: 7 )