By Topic

Analysis and simulation of distortion in folding and interpolating A/D converters

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Limotyrakis, S. ; Center for Integrated Syst., Stanford Univ., CA, USA ; KiYoung Nam ; Wooley, B.A.

A method for analyzing distortion in a complementary metal-oxide-semiconductor (CMOS) analog-to-digital (A/D) converter with continuous-time folding and interpolation is presented. Distortion resulting from limited bandwidth at the output of the folders, interpolation at the output of the folders, and comparator offset are considered. Simulation results are presented for a range of architectural configurations, and means of extending the method to include the effect of other nonidealities are considered. The present analysis can be used to estimate distortion in A/D converters employing continuous-time folding and aid in the decision of whether to incorporate a track-and-hold circuit at the input of the converter

Published in:

Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on  (Volume:49 ,  Issue: 3 )