Analysis and simulation of distortion in folding and interpolating A/D converters

A method for analyzing distortion in a complementary metal-oxide-semiconductor (CMOS) analog-to-digital (A/D) converter with continuous-time folding and interpolation is presented. Distortion resulting from limited bandwidth at the output of the folders, interpolation at the output of the folders, and comparator offset are considered. Simulation results are presented for a range of architectural configurations, and means of extending the method to include the effect of other nonidealities are considered. The present analysis can be used to estimate distortion in A/D converters employing continuous-time folding and aid in the decision of whether to incorporate a track-and-hold circuit at the input of the converter.