Yield enhancement of 128M SDRAM by RTA/RTO process combination to suppress the sidewall defects of polycide gate conductor

Integrated polysilicon and metal silicide stack has been adopted by worldwide DRAM designers as the gate conductor material to reduce the wordline sheet resistance. Unfortunately, abnormal gate profile resulted from sidewall defects under thermal stress would make an impact on the window of process integration and even the final wafer yield. In this study, we have examined the correlation of sidewall defect formation and key parameters of rapid thermal oxidation like oxygen concentration in low temperature annealing and x ratio of WSix films. A new combined RTA/RTO process was proposed to solve this problem and got a significant yield improvement as compared with integrated RTA/RTO process.