High performance ultra-thin silicon nitride gate dielectrics prepared by in-situ RTCVD techniques

Through the characterization of RTCVD process conditions, high performance CMOS devices based on silicon nitride stack gate dielectrics with 40 nm gate length were prepared. In sub 20 /spl Aring/ thick ultra-thin stack gate dielectrics approaching 12 /spl Aring/ of EOT, it was found that HF last cleaned dielectric layer shows slightly higher leakage current as compared to the conventional RCA cleaned dielectric layer. It may be due to thinner dielectric properties on HF last cleaned surfaces. It was also found that annealing with NO, N/sub 2/O and N/sub 2/ modifies the bonding structure of silicon nitride stack layers and significantly improved the properties of ultra-thin stack gate dielectrics.