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Driving 100 nm and below 300 mm manufacturing solutions - an era of single wafer processing, factory efficiencies, and new materials and technology introductions at reduced thermal budget and improved cycle time

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5 Author(s)
Gronet, C. ; Transistor & Capacitor Product Bus. Group, Appl. Mater. Inc., Santa Clara, CA, USA ; Meissner, P. ; Truman, K. ; Miner, G.
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We discuss the key device technology and manufacturing challenges confronting the semiconductor industry as it progresses towards the 100 nm node and implement 300 mm wafer size in volume manufacturing. Front end of the line (FEOL) modules related to substrate engineering, low thermal budget processing and junction formation, isolation and STI module, transistor challenges for gate dielectrics, gate electrodes, and capacitor formation for DRAM are discussed with single wafer processing as the core capability. Two themes are evident as we progress towards the 100 nm device node: the trend toward single-wafer processing and the emerging potential for using integrated equipment sets, or modules, to create some of the structures in the FEOL area in general and the transistor and capacitor regions in particular. In this paper, we provide an overview of some of the state-of-the-art developments in the FEOL arena and highlight the yield boosting solutions and strategies to provide the desired process capability primarily directed towards volume manufacturing.

Published in:

Advanced Thermal Processing of Semiconductors 9th Internationa Conference on RTP 2001

Date of Conference:

2001