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Long pipelines in single-chip digital signal processors-concepts and case study

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1 Author(s)
Ernst, R. ; Inst. of Tech. Electron., Erlangen-Nuremberg Univ., Germany

The effectiveness of long pipelines in single-chip digital signal processors for complex algorithms was studied using a processor model with 25 pipeline stages. The processor is based on a Harvard architecture. Pipelining is used to reduce the instruction cycle time compared to current signal processors. Key features of the processor model are data-stationary pipeline control, local resolution of pipeline hazards with buffering, multiple branch prediction, a mixed relative-incremental addressing scheme, and asynchronous communication between pipeline and environment. The processor is implemented as a software model. The results show that high pipeline utilization can be achieved for a variety of algorithms leading to a significantly higher performance than achieved by conventional single-chip signal processors with Harvard architecture

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Circuits and Systems, IEEE Transactions on  (Volume:38 ,  Issue: 1 )