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In this paper, we introduce a computing technique based on a genetic algorithm (GA) built to first evolve, then learn the logic circuits of defined functions. An input model represents the problem being resolved, and the system evolves a solution using a hardware-based GA. The presented work is part of the ongoing research in the concept of intelligent architectures, first presented by Rami Abielmona (2002), based on the merge of evolvable hardware methodologies and reconfigurable computing approaches. The system, named Genetic algorithm Synthesis, has been realized and analyzed, with the results presented in this paper. The major finding is that the system is able to find a minimized representation of the circuit, based on the ideas of functional decomposition of boolean literals and technology mapping on a field programmable gate array. The system not only finds a minimized structure,, but multiple minimal structures, thus allowing the environment to control which structure is reconfigured on the device, based on external factors such as temperature, available area and/or memory and required speed.