By Topic

Efficient parallel implementation of motion estimation on the Computational RAM architecture

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

5 Author(s)
Ai, H. ; Dept. of Electr. & Comput. Eng., Alberta Univ., Edmonton, Alta., Canada ; Li, N. ; Li, T. ; Mandal, M.K.
more authors

Motion estimation is the most computationally intensive task in present video compression standards. Parallel processing has proved to be an efficient approach for similar kinds of applications. In this paper, we propose two parallel implementations of block-based motion estimation for a massively-parallel, processor-in-memory hardware architecture known as Computational RAM (C-RAM). Our simulation study showed that, although the massive parallelism of C-RAM does potentially have great benefits, the use of embedded DRAM and bit-serial arithmetic reduced the achievable speed-up to about 4 compared to 733 MHz Pentium III machine.

Published in:

Electrical and Computer Engineering, 2002. IEEE CCECE 2002. Canadian Conference on  (Volume:2 )

Date of Conference:

2002