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Modeling substrate noise generation in CMOS digital integrated circuits

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3 Author(s)
Makoto Nagata, ; Integrated Syst. Lab., Hiroshima Univ., Japan ; Morie, T. ; Iwata, A.

A time-series divided parasitic capacitance model accurately simulates substrate noise generation of practical CMOS digital integrated circuits in the time domain. The simulation of a 0.25-μm z80 microcontroller with 62.5-MHz clock frequency costs less than 10 sec per a clock cycle including the model generation. Simulated substrate noise compares well with 200-ps 100-μV resolution measurements in wave-shapes validated for clock frequency up to 125 MHz and shows a peak-amplitude error of less than 2% against supply-voltage scaling from 2.5 V to 1.6 V.

Published in:

Custom Integrated Circuits Conference, 2002. Proceedings of the IEEE 2002

Date of Conference:

2002