By Topic

Modeling substrate noise generation in CMOS digital integrated circuits

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
M. Nagata ; Integrated Syst. Lab., Hiroshima Univ., Japan ; T. Morie ; A. Iwata

A time-series divided parasitic capacitance model accurately simulates substrate noise generation of practical CMOS digital integrated circuits in the time domain. The simulation of a 0.25-μm z80 microcontroller with 62.5-MHz clock frequency costs less than 10 sec per a clock cycle including the model generation. Simulated substrate noise compares well with 200-ps 100-μV resolution measurements in wave-shapes validated for clock frequency up to 125 MHz and shows a peak-amplitude error of less than 2% against supply-voltage scaling from 2.5 V to 1.6 V.

Published in:

Custom Integrated Circuits Conference, 2002. Proceedings of the IEEE 2002

Date of Conference: