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High-input-sensitivity, low-power 43 Gbit/s decision circuit using InP/InGaAs DHBTs

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7 Author(s)
Ishii, K. ; Res. Center for Integrated Quantum Electron., Hokkaido Univ., Sapporo ; Nosaka, H. ; Ida, M. ; Kurishima, K.
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A high-input-sensitivity, low-power decision circuit for 40 Gbit/s-class optical communications systems using InP/InGaAs double-heterojunction bipolar transistors (DHBTs) has been designed and fabricated. These DHBTs exhibit an fT of 131 GHz and an fmax of 191 GHz at a collector current density of 0.5 mA/μm2 and a collector-to-emitter voltage of 1.2 V. The decision circuit was operated at a data rate of up to 43 Gbit/s with a low power consumption of 0.7 W. A high input sensitivity of 50 mV and a wide clock phase margin of 201° at 43 Gbit/s were achieved

Published in:

Electronics Letters  (Volume:38 ,  Issue: 12 )