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The system design and the chip implementation aspects of an MPEG1/2 audio layer 3 (MP3) decoder chip suitable for Compact Disc (CD) based systems is discussed. A new innovative chip architecture is presented which addresses the low-power requirements of portable applications. This utilizes an optimum split between control processing tasks and signal processing code. The architecture was implemented using a synthesizable System-on-a-Chip approach. The chip has been fabricated in 0.18 μm CMOS technology. The silicon area is 16 mm2 and operates at a minimum of 140 MHz, achieving up to 80 hours of playtime. This low-power approach outperforms other commercially available solutions.