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A general probabilistic framework for worst case timing analysis

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2 Author(s)
Orshansky, M. ; Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA ; Keutzer, K.

The traditional approach to worst-case static-timing analysis is becoming unacceptably conservative due to an ever-increasing number of circuit and process effects. We propose a fundamentally different framework that aims to significantly improve the accuracy of timing predictions through fully probabilistic analysis of gate and path delays. We describe a bottom-up approach for the construction of joint probability density function of path delays, and present novel analytical and algorithmic methods for finding the full distribution of the maximum of a random path delay space with arbitrary path correlations.

Published in:

Design Automation Conference, 2002. Proceedings. 39th

Date of Conference:

2002