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Total power optimization by simultaneous dual-Vt allocation and device sizing in high performance microprocessors

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8 Author(s)
Karnik, T. ; Circuit Res., Intel Labs., Hillsboro, OR, USA ; Yibin Ye ; Tschanz, J. ; Liqiong Wei
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We describe various design automation solutions for design migration to a dual-Vt process technology. We include the results of a Lagrangian relaxation based tool, iSTATS, and a heuristic iterative optimization flow. Joint dual-Vt allocation and sizing reduces total power by 10+% compared with Vt allocation alone, and by 25+% compared with pure sizing methods. The heuristic flow requires 5× larger computation runtime than iSTATS due to its iterative nature

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Design Automation Conference, 2002. Proceedings. 39th

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