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In this paper we propose a novel integrated circuit and architectural level technique to reduce leakage power consumption in high performance cache memories using a single Vt (transistor threshold voltage) process. We utilize the concept of gated-ground (an NMOS transistor inserted between the ground line and SRAM cell) to achieve a reduction in leakage energy without significantly affecting performance. Experimental results on gated-ground caches show that data are retained (DRG-cache) even in stand-by mode of operation. Data are restored when the gated-ground transistor is turned on. Turning off the gated-ground transistor in turn gives a large reduction in leakage power. This technique requires no extra circuitry; the row decoder itself can be used to control the gated-ground transistor. The technique is applicable to data and instruction caches as well as different levels of cache hierarchy such as the L1, L2, or L3 caches. We fabricated a test chip in TSMC 0.25 μ technology to show the data retention capability and the cell stability of DRG-cache. Our simulation results on 100 nm and 70 nm processes (Berkeley Predictive Technology Model) show 16.5% and 27% reduction in consumed energy in L1 cache and 50% and 47% reduction in L2 cache with less than 5% impact on execution time and within 4% increase in area overhead.