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Power estimation in global interconnects and its reduction using a novel repeater optimization methodology

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3 Author(s)
Kapur, Pawan ; Dept. of Electr. Eng., Stanford Univ., CA, USA ; Chandra, G. ; Saraswat, K.C.

The purpose of this work is two fold: first, to quantify and establish future trends for dynamic power dissipation in global wires of high performance integrated circuits; and second, to develop a novel and efficient delay-power tradeoff formulation for minimizing power due to repeaters, which can otherwise constitute 50% of total global wire power dissipation. Using the closed form solutions from this formulation, power savings of 50% on repeaters are shown with minimal delay penalties of about 5% at the 50 nm technology node. These closed-form, analytical solutions provide a fast and powerful tool for designers to minimize power.

Published in:

Design Automation Conference, 2002. Proceedings. 39th

Date of Conference:

2002