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Thermal deformation analysis on flip-chip packages using high resolution moire interferometry

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4 Author(s)
Guotao Wanga ; Mater. Sci. Lab. for Interconnect & Packaging, Texas Univ., Austin, TX, USA ; Jie-Hua Zhao ; Min Ding ; Ho, Paul S.

Solder reliability has been an issue with many fine-pitch, area-array packages because of the large thermal expansion (CTE) mismatch between the silicon die and the substrate. One solution to flip-chip plastic ball grid array (FCPBGA) package is to underfill the solder bumps to improve the reliability by reducing the solder bump shear stresses. However, for an underfilled flip-chip package, large thermal stresses will develop along the solder bump-underfill during thermal cycling due to the materials discontinuity. Delamination along the die-underfill interface has often been found in reliability test. In this study, high-resolution moire interferometry was used to investigate the thermal deformations for some experimental flip-chip packages. Experimental details of high-resolution moire interferometry are presented. Using a phaseshift technique, the resolution of moire interferometry is achieved at 26 nm per fringe order. Displacement and, especially, the strain distribution can be obtained accurately at this resolution. This experimental technique can analyze deformations with small features, such as the C4 bumps and high density interconnect (HDI) structure. Experimental results for HDI FCPBGA packages are presented and discussed.

Published in:

Thermal and Thermomechanical Phenomena in Electronic Systems, 2002. ITHERM 2002. The Eighth Intersociety Conference on

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