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Damascene copper is rapidly replacing aluminum as the interconnect material of choice in silicon technology. The change is driven by the lower electrical resistivity of copper, which decreases power consumption and permits increased central processor unit (CPU) clocking speeds. Electroplating is the preferred deposition method because it permits filling of high-aspect ratio features without seams or voids through the process of superconformal deposition, also called "superfill." This process has been demonstrated to depend critically on the inclusion of additives in the electrolyte. Superfill occurs when a high aspect ratio feature on a silicon wafer fills due to preferential metal deposition permitting the bottom surface to rise before the side walls close off. Two crucial mechanisms by which the additives enable superfill to occur are (a) accelerator behavior increasing the copper deposition rate as a function of coverage and (b) conservation of accelerator coverage with increasing/decreasing arc length. A model that includes these effects is implemented using the level set method. Trench superfilling simulations will be presented and compared with experiment.