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This paper describes the results of a computational investigation of the thermal performance of chip scale package arrays with various low profile heat sinks. The arrays considered were fully populated with both modules and heat sinks. The heat sinks used in any single array were identical. The parameters evaluated included module spacing, cooling air inlet velocity, per module power dissipation, and heat sink design. The heat sinks fell into two categories: the plate and the block. A plate was defined as a single continuous piece of material covering all of the modules in the array. The block heat sinks were individual pieces of material that were affixed to each module and were not physically connected to the other heat sinks in the array. The results of this study are presented as thermal resistances for each module in the array. Also considered, for some specific cases, are the heat transfer coefficients for each heat sink as a function of its position within the array. Interesting results included the changing of the shape of the resistance curve with changes in heat sink design. Also noted was the relationship between the thermal resistance of a module and the heat transfer coefficient for the top surface of that heat sink. Related to this were the changes in thermal resistance due to changes in the material properties used in the modules and how this affected the heat flow within the array.