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A robust high voltage Si LDMOS model extraction process to achieve first pass linear RFIC amplifier design success

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2 Author(s)
Pla, J.A. ; Semicond. Products Sector, Motorola Inc., Tempe, AZ, USA ; Bridges, D.

A robust model extraction procedure was developed for a high voltage Si LDMOS RFIC process to achieve first pass linear RFIC amplifier design success. The model extraction process utilizes pulsed isothermal small-signal S-parameter measurements and extracted large-signal Root Models at three different temperatures to extract model parameters for Motorola's Electro-Thermal (MET) FET analytical model. Large-signal model validation was performed against loadpull measurements under 1-tone and 2-tone stimuli. Also, the models were developed into a design kit within Agilent/sup (R)/ EEsof/sup (R)/'s ADS/sup (R)/ (Advanced Design System) to design a wide-band 30 Watt power amplifier IC which achieved first pass design success.

Published in:

Radio Frequency Integrated Circuits (RFIC) Symposium, 2002 IEEE

Date of Conference:

3-4 June 2002