By Topic

A comparison of methods for total dose testing of bulk CMOS and CMOS/SOS devices

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Baze, M.P. ; Boeing Aerosp. & Electron., Seattle, WA, USA ; Plaag, R.E. ; Johnston, A.H.

Low- and high-dose-rate testing results are compared for CMOS technologies. The long-term experiments extend over time periods of more than one year so that comparisons could be made over time frames more nearly like those in the space environment. High-temperature annealing is evaluated as a means of accelerating the annealing time and predicting low-dose-rate results. The data on hardened CMOS and CMOS/SOS devices show that for these particular processes, annealing at 100°C did not accelerate trapped hole annealing. Differences between expected and actual results are identified, and recommendations are made for improving test procedures

Published in:

Nuclear Science, IEEE Transactions on  (Volume:37 ,  Issue: 6 )