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A low jitter 5.3-GHz 0.18-/spl mu/m CMOS PLL based frequency synthesizer

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2 Author(s)
Ali, S. ; Dept. of Electr. & Comput. Eng., Connecticut Univ., Storrs, CT, USA ; Jain, F.

A 5.3-GHz CMOS phase locked loop (PLL) based frequency synthesizer is reported. The PLL operates as an integer-N frequency synthesizer using a ring-type voltage controlled oscillator (VCO). The PLL based synthesizer operates from 4.9 to 5.3-GHz and achieves a phase noise of -121.9 dBc/Hz at 10-MHz offset frequency from the carrier for maximum oscillation frequency of 5.3-GHz. The ring VCO works from 4.21 to 5.46-GHz with a maximum power consumption of 4.7-mW. A completely ripple-free VCO control voltage is obtained using a current mirror current source in a charge pump loop filter. The PLL is implemented with TSMC 0.18-/spl mu/m technology for GSM applications. The output rms jitter is 0.3% of the oscillator period. The total power consumption of this synthesizer is only 10-mW from a 1.8 V power supply.

Published in:

Radio Frequency Integrated Circuits (RFIC) Symposium, 2002 IEEE

Date of Conference:

3-4 June 2002