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The performance of a novel current-steering logic sense-amplifier (CSL-SA) is verified through measurements in 0.18 μm CMOS by implementing a CSL-SA flip-flop (CSL-SAFF). The measured operating frequency of 3.3 GHz in 0.18 μm is the highest performance results published to date in any CMOS technology. Measurements using 0.5, 0.35, 0.25 and 0.18 μm technologies show power and speed scaling of the new SA and SAFF to smaller geometries. The CSL-SA has better input sensitivity and 92% less clock-load compared to conventional voltage SAs.
Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on (Volume:2 )
Date of Conference: 2002