Design and implementation of a continuous-time quadrature bandpass sigma-delta modulator for low-IF radio receivers

This paper presents the first continuous-time implementation of a quadrature bandpass ΣΔ modulator. This new architecture needs no additional anti-aliasing filter in contrast to former switched-capacitor designs. Furthermore it is shown that the performance of this second-order ΣΔ modulator is less sensitive to channel mismatch and excess loop delay as comparable designs. The ΣΔ modulator has a bandwidth of 1 MHz, centered at 1 MHz, and achieves a peak SNDR of 56.2 dB at 100 MHz clock frequency. The ΣΔ modulator has been implemented in a 0.65 μm BiCMOS technology and consumes 21.8 mW at 2.7 V.