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A 3.3-V 18-bit digital audio Sigma-Delta modulator in 0.6-μm CMOS

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4 Author(s)
Yavari, M. ; Electr. & Comput. Eng. Dept., Tehran Univ., Iran ; Hasanzadeh, M.R. ; Talebzadeh, J. ; Shoaei, O.

This paper presents a 3.3-V, 18-bit Sigma-Delta modulator for digital audio, which has been simulated in a 0.6 μm double poly, triple metal CMOS process using poly-poly capacitors in all process corners and considering ± 10 % power supply and -40°C to 85°C temperature ranges. The integral gain coefficients of a 2-2 cascaded modulator have been developed for achieving higher overload level factor that is needed for high-resolution noise limited performance modulators. Simulation results give SNDR of 111 dB and 110 dB in typical and worst case, respectively with considering of the circuit noise.

Published in:

Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on  (Volume:2 )

Date of Conference:

2002