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A method of test generation for path delay faults in balanced sequential circuits

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3 Author(s)
Ohtake, S. ; Graduate Sch. of Inf. Sci., Nara Inst. of Sci. & Technol., Japan ; Miwa, S. ; Fujiwara, H.

This paper shows that path delay fault test generation problem for sequential circuits with balanced structure can be reduced to segment delay fault test generation problem for their combinationally transformed circuits. We also propose a test generation method and a partially enhanced scan design method for path delay fault.

Published in:

VLSI Test Symposium, 2002. (VTS 2002). Proceedings 20th IEEE

Date of Conference:

2002

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