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Speeding up the Byzantine fault diagnosis using symbolic simulation

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1 Author(s)
Shi-Yu Huang ; Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan

Fault diagnosis is to predict the potential fault sites in a logic IC. In this paper, we particularly address the problem of diagnosing faults that exhibit the so-called Byzantine General's phenomenon, in which a fault manifests itself as a non-logical voltage level at the fault site. Previously, explicit enumeration was suggested to deal with such a problem. However, it is often too time-consuming because the CPU time is exponentially proportional to fanout degree of the circuit under diagnosis. To speed up this process, we present an implicit enumeration technique using symbolic simulation. Experimental results show that the CPU time can be improved by several orders of magnitude for ISCAS85 benchmark circuits.

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VLSI Test Symposium, 2002. (VTS 2002). Proceedings 20th IEEE

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