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A current-mode folding/interpolating CMOS analog to quaternary converter using binary to quaternary encoding block

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4 Author(s)
Sung Il Han ; Dept. of Electron. Eng., Inha Univ., Incheon, South Korea ; Seung Yong Park ; Hyeon Kyeong Seong ; Heung Soo Kim

A current-mode folding and interpolating analog to quaternary digital converter (AQC) with binary to quaternary encoder has been proposed in this paper. A current-mode three-level folding amplifier has been employed to reduce the number of reference current sources and a low impedance current-mode approach is adopted. A voltage level converter circuit has been proposed not only to encode the binary output signal to the quaternary output signal, but also to enable the proposed AQC to be applied as a starting point device of the quaternary logic. Fast settling time and low power consumption of the AQC are achieved by utilising the proposed architecture. The simulation results of the designed 4 digit AQC show a sampling rate of 14 MHz and a power dissipation of 150 mW with a single power supply of 3.3 V for a double poly four metal standard CMOS 0.35 μm n-well technology

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Multiple-Valued Logic, 2002. ISMVL 2002. Proceedings 32nd IEEE International Symposium on

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