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Parallel evolutionary graph generation on a PC cluster and its application to multiple-valued circuit synthesis

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3 Author(s)
Natsui, M. ; Graduate Sch. of Inf. Sci., Tohoku Univ., Sendai, Japan ; Aoki, T. ; Higuchi, T.

This paper presents an efficient graph-based evolutionary optimization technique called evolutionary graph generation (EGG) and its extension to a parallel version. The parallel EGG system presented in this paper is based on a coarse-grained model of parallel processing and is implemented on a 16-node Linux PC cluster. The potential capability of parallel EGG system is demonstrated through the synthesis of a radix-4 signed-digit (SD) full adder circuit

Published in:

Multiple-Valued Logic, 2002. ISMVL 2002. Proceedings 32nd IEEE International Symposium on

Date of Conference:

2002