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A hierarchical interface design methodology and models for SoC IP integration

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3 Author(s)
Jer-Min Jou ; Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan ; Shiann-Rong Kuang ; Kuang-Ming Wu

A key aspect of an IP core's marketability is its ability to be easily integrated across a wide variety of interfaces. In this paper, we propose an efficient hierarchical interface design methodology and models so that a designer can quickly design an IP core's interface, which can be easily integrated into any interface/bus architecture. The proposed methodology and models have been applied to design an MP3 decoder with different interfaces: an ISA bus interface and a PCI bus interface. The results demonstrate that the methodology and models result in easy IP integration and only a little performance overhead

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Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on  (Volume:2 )

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