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An efficient architecture for two-dimensional inverse discrete wavelet transform

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3 Author(s)
Po-Cheng Wu ; Network Commun. Lab., Inst. for Inf. Ind., Taipei, Taiwan ; Chao-Tsung Huang ; Liang-Gee Chen

This paper proposes an efficient architecture for the two-dimensional inverse discrete wavelet transform (2D IDWT). The proposed architecture includes an inverse transform module, a RAM module, and a multiplexer. In the inverse transform module, we employ the coefficient folding technique and the polyphase decomposition technique to the interpolation filters of stages 1 and 2, respectively. The RAM size is N/2×N/2. The advantages of the proposed architecture are the 100% hardware utilization, fast computing time, regular data flow, and low control complexity, making this architecture suitable for next generation image coding/decoding systems.

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Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on  (Volume:2 )

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