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Floating gate analog implementation of the additive soft-input soft-output decoding algorithm

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2 Author(s)
A. F. Mondragon-Torres ; Dept. of Electr. Eng., Texas A&M Univ., College Station, TX, USA ; E. Sanchez-Sinencio

The soft-input soft-output decoding algorithm is used to decode concatenated codes iteratively. To implement this algorithm efficiently, an additive form in the logarithmic domain is employed. A novel analog implementation using CMOS translinear circuits is proposed. A multiple-input floating-gate CMOS transistor working in the subthreshold region is used as the main translinear computing element. The proposed approach allows a direct mapping between the decoding algorithm and the circuit implementation. Experimental CMOS chip results are in good agreement with theoretical and simulation results

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Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on  (Volume:2 )

Date of Conference: