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Designing multiplier blocks with low logic depth

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3 Author(s)
Dempster, A.G. ; Univ. of Westminster, London, UK ; Dimirsoy, S.S. ; Kale, I.

The depth of logic in an integrated circuit, particularly a CMOS circuit, is highly correlated both with power consumption and degraded switching speed. Hence, designs with low logic depth can aid in reducing power consumption and increasing switching speed. In this paper we demonstrate how new and modified algorithms have been used to design multiplier blocks with low logic depth and power consumption.

Published in:

Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on  (Volume:5 )

Date of Conference:

2002