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Low-power register-exchange Viterbi decoder for high-speed wireless communications

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2 Author(s)
D. A. F. Ei-Dib ; VLSI Res. Group, Waterloo Univ., Ont., Canada ; M. I. Elmasry

A new implementation for the Viterbi (1967) decoder (VD) based on the register-exchange (RE) method is described. Conceptually, the RE method is simpler and faster than the traceback (TB) method, but its disadvantage is that every bit in the memory must be read and rewritten for each bit decoded. Using the 'pointer' concept; a pointer is assigned to each register. Instead of copying the contents of one register to another, the pointers are modified. Power dissipation, performance, memory size, and the speed of the survivor memory unit (SMU) are analyzed for both the proposed RE method and the TB method, described in the literature for the next generation wireless applications. The new implementation shows an average power reduction of 45 percent. The BER is 10-5 at a SNR around 6.1 dB for a continuous uncontrolled encoded sequence. The memory is reduced by half and all read and write operations in the SMU are executed at the data rate frequency.

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Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on  (Volume:5 )

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