By Topic

Low-power register-exchange Viterbi decoder for high-speed wireless communications

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
D. A. F. Ei-Dib ; VLSI Res. Group, Waterloo Univ., Ont., Canada ; M. I. Elmasry

A new implementation for the Viterbi (1967) decoder (VD) based on the register-exchange (RE) method is described. Conceptually, the RE method is simpler and faster than the traceback (TB) method, but its disadvantage is that every bit in the memory must be read and rewritten for each bit decoded. Using the 'pointer' concept; a pointer is assigned to each register. Instead of copying the contents of one register to another, the pointers are modified. Power dissipation, performance, memory size, and the speed of the survivor memory unit (SMU) are analyzed for both the proposed RE method and the TB method, described in the literature for the next generation wireless applications. The new implementation shows an average power reduction of 45 percent. The BER is 10-5 at a SNR around 6.1 dB for a continuous uncontrolled encoded sequence. The memory is reduced by half and all read and write operations in the SMU are executed at the data rate frequency.

Published in:

Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on  (Volume:5 )

Date of Conference:

2002