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A new hardware efficient design for the one dimensional discrete Fourier transform

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2 Author(s)
Jiun-In Guo ; Dept. of Comput. Sci. & Inf. Eng., Nat. Chung Cheng Univ., Chia Yi, Taiwan ; Chien-Chang Lin

This paper presents a new hardware efficient design for the one-dimensional (1D) discrete Fourier transform (DFT). By combining the advantages of distributed arithmetic (DA) computation and features of the cyclic convolution, we can efficiently realize the 1D N-point DFT using small ROM modules and accumulators. To increase the ROM utilization, we first make all the N ROM modules identical and only share a ROM module in computing all the DFT outputs. Besides, we apply the ROM partition to further reduce the ROM cost with the overhead of slowing down the speeds. This hardware efficient feature is very useful in realizing the long length DFT with critical hardware requirement. Comparison results with the traditional DA-based designs show that the proposed design can reduce the ROM cost exponentially.

Published in:

Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on  (Volume:5 )

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