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We present the design of a linear array of CMOS optical receivers for inter-chip communication in advanced computer architectures. We consider architectures, circuit techniques, and design constraints particular to silicon on sapphire (SOS) receivers. The receivers are fabricated in 0.5 μm Ultra-Thin Silicon on Sapphire (Utsi) CMOS which enables the design of high speed circuits with low power consumption and low substrate cross-talk. Each channel of the array consumes 5 mW of power from a 3.3 V supply, and operates up to 500 MHz.