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A low-power subscriber line interface circuit in a high-voltage CMOS technology

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3 Author(s)
Vahidfar, M. ; Dept. of Electr. Eng., Sharif Univ. of Technol., Tehran, Iran ; Tajalli, A. ; Atarodi, M.

A low-power CMOS Subscriber Line Interface Circuit (SLIC) in a 1 μm high voltage technology is presented. A systematic approach to extract the necessary specification for each block to achieve stability, accuracy, and other desired SLIC characteristics is applied. For this purpose a proper sense and feed system is introduced. The proposed SLIC shows a longitudinal balance of 53.7 dB while consumes 2.5 mA current with 16 mm2 area. This transformer-less SLIC met transmission specifications without trimming.

Published in:

Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on  (Volume:5 )

Date of Conference:

2002