A low-power subscriber line interface circuit in a high-voltage CMOS technology

A low-power CMOS Subscriber Line Interface Circuit (SLIC) in a 1 /spl mu/m high voltage technology is presented. A systematic approach to extract the necessary specification for each block to achieve stability, accuracy, and other desired SLIC characteristics is applied. For this purpose a proper sense and feed system is introduced. The proposed SLIC shows a longitudinal balance of 53.7 dB while consumes 2.5 mA current with 16 mm/sup 2/ area. This transformer-less SLIC met transmission specifications without trimming.